• Tap the superior performance of FPGA Architecture Specific Technology synthesis
  Since OrCAD Express was introduced two years ago, thousands of designers have adopted it for programmable logic and system design. Design engineers appreciate the ease with which they can incorporate VHDL throughout the design process. They stress that Express is the first tool that truly enables them to adopt a new language without impacting design schedules.

  As VHDL is used more and more to model the functionality of the programmable device and displaces schematic-based circuitry, the synthesis phase is becoming a bottleneck to the design flow. By incorporating Exemplar Logic's F.A.S.T. (FPGA Architecture Specific Technology) optimization, OrCAD Express designers will enjoy dramatically reduced run times and extract the highest quality of results.

• Target high-capacity ASIC-replacement or prototype FPGAs
  Today's engineering departments are striving to increase operating frequency, reduce component counts, and increase the capacity of digital systems. They are using high-density FPGAs more frequently to consolidate multiple lower density FPGAs and CPLDs or to replace circuitry traditionally implemented into ASICs. By incorporating superior synthesis and further investments in VHDL simulation by OrCAD, Express provides the ability to target VHDL-based designs into ASIC-replacement FPGAs like the Xilinx SPARTAN, Altera FLEX 10K, or Actel MX, without fear of decreased performance from the EDA tool.
• Support the intellectual property (IP) of your engineering department
  One of the key benefits of VHDL for digital design is the way it enables engineering departments to maintain a library of common hardware functions. These libraries promote reuse, lessen duplication of design effort, and provide a common standard for inter-division communication. Logic synthesis powered by Exemplar Logic, Express will offer the richest set of synthesizable VHDL constructs in the industry, so designers can take full advantage of their expressive power. Supported VHDL constructs include configuration declaration statements, multi-dimensional arrays, recursive functions, and record types. Express is also compatible with popular VHDL arithmetic packages from Synopsys and Exemplar Logic.

New programmable logic vendor support

Other new features

• Faster simulations. Get to your answers faster and more reliably with the VHDL-based digital simulator. Express's simulator has demonstrated 10-30% faster run time on many FPGA design benchmarks. Debug VHDL source before logic synthesis or check the performance of your chip after place-and-route faster than ever before.
• Improved stimulus tool. Create internal or external signal stimulus easier and faster with new interactive stimulus "force" and "remove" commands. Express's simulator enables the creation of more elaborate circuit tests such as "what-if" situations to emulate internal glitch conditions, temporary reset pulses, or bi-directional data bus interactions.

• New VHDL signal or variable query feature. Interpret how VHDL signals or variables are used in your design. Understand what caused a state by viewing the driver, or how a state could impact signals or variables downstream by the reader list. Express's simulator displays important debugging data in a new display which illustrates the declaration, file location, reader and driver list of any signal or variable.

• Using long file names with Xilinx Alliance Series (M1) software. If you are running Xilinx Alliance Series software remotely (over a network) be sure that the Xilinx software is installed in a v8.3 compatible directory. That is, be sure that the path to the software does not include spaces or long file names. This has been known to cause problems.

• Load time error with EXEMPLAR_1164 (from EX_1164.VHD) shift and multiplication functions. Simulate does not support the functions SL, SL2, SR2, MULT, and MULT2 when used in conjunction with a slice operation. For example, if the design uses a shift function with a constant array that has a size and value that is dependent on the size and value of a formal parameter, and then later in the function that constant array is sliced with an expression based on another formal parameter, an error will be generated.
  

  Fatal error is slice code generation at line n.file_name.vhd : compile failed in Note. Project Load Failed

• ABS() function. The Absolute value (ABS()) function from the EXEMPLAR_1164 package may cause a runtime crash. To work around the problem, set the type of the EX_1164.VHD file to "VHDL netlist" using the project manager's Properties command.
• Unexpected results from EXEMPLAR_1164 (from EX_1164.VHD) with extend() and extend 2(). Simulate does not support the truncation usage of zero-extend functions.

• Product configurations: Programmable logic vendor support, pages xi and xii.
• The Express column should include Xilinx XC3x00A/L, XC5200, XC4000E/L, XC4000X, XC9500, and SPARTAN.

• The Express Plus column should include Xilinx VIRTEX.
• Related documentation, page xv.
  • The multi-media VHDL tutorial is actually the Esperan MasterClass. This is a Windows-based tutorial for FPGA and PLD design.

• Support for designing programmable logic, page 6.

  • The string "Express includes Exemplar Logic's Leonardo Spectrum logic synthesis..." should read "Express includes logic synthesis powered by Exemplar Logic."

• Local synthesis and optimization constraints, page 113.

  • The EXEMPLAR package (of file EXEMPLAR.VHD) defines a large set of functions for both the standard BIT and BIT_VECTOR data types. For backwards compatibility, these functions are also defined for ELBIT and ELBIT_VECTOR types. The example library and usage clause:

    library EXEMPLAR; use EXEMPLAR.EXEMPLAR.all;

  • All functions are also defined with the IEEE 1164 types STD_LOGIC, STD_ULOGIC, STD_LOGIC_VECTOR, and STD_ULOGIC_VECTOR in the package EXEMPLAR_1164 of file EX_1164.VHD. The example library and usage clause:

    library EXEMPLAR; use EXEMPLAR.EXEMPLAR_1164.all;

• When Simulate and Capture are open simultaneously, with Intertool Communication (ITC) enabled, program performance and response time may be affected when you edit your schematic, especially for large designs with complex hierarchy. If you observe this, you can temporarily disable ITC to improve performance. OrCAD recommends that you only run ITC when you interactively troubleshoot your design, not when you edit it.

• Release 9 includes changes to the interactive stimulus editor. All interactive stimuli are now considered forces that override propagated signals and test benches. There is also a new feature that allows you to remove a stimulus from the circuit and return the signal value to the propagation of the circuit.

• Release 9 also allows for stimulus retargetting when the design hierarchy changes. Specifically, it is no longer necessary to recreate interactive stimulus files just because the design hierarchy has changed between simulation sessions. In Release 9, when the stimulus file is loaded, Simulate checks to make sure that each stimulus defined therein can be mapped to a signal in the currently loaded design. When a stimulus does not correspond to a signal in the design, you are given the option to retarget that stimulus to another signal in the design.

• Complied simulation is no longer supported.

• VHDL network and process initialization has been corrected. As a result, circuits that gave seemingly good results in previous versions (especially on INOUT ports) may now (correctly) show those values as uninitialized.

• Important defects in previous versions of Express Simulate that are addressed in Release 9:
  • SCR2273 Passing variable into the TO_UNSIGNED() function of the NUMERIC_STD package fails.

  • SCR4420 Reinitialization of REAL or INTEGER data type variables fails.

  • SCR4393 Type conversion between REAL and INTEGER as part of an association list fails.

  • SCR4535 Size check of non-array object fails.

  • SCR4673 Subscripted aliases of other aliases fails.

  • SCR4799 Unexpected states ('X') after reload.

  • SCR4904 Array assignment with functions fails.

  • SCR4932 Local variable sizing problem can cause endless loop condition.

  • SCR5073 Condition which causes: "Bad type " for this context" error corrected.

  • SCR5134 Certain assert, reload sequences fail.

  • SCR5149 Models with large number of data objects fail.

  • SCR5172 Aggregates with OTHERS=> clause fail.

  • SCR5185 Incorrect simulation with Actel ACT2 bidirectional models.

  • SCR5249 Timed simulations that include more than 24 SDF entries per design unit fail.

  • SCR5258 Bad object in sensitivity list fails.

  • SCR5281 MINC VITAL/VHDL models fail to load.

OrCAD recommends that you archive and maintain all programmable logic projects developed with OrCAD Express for Windows Version 7.20 and use OrCAD Express Release 9 for new development efforts only. If you open a project created by Version 7.20, OrCAD Capture Release 9 will report:

Warning: This project was created with an earlier version of OrCAD Express. Due to changes in library and project settings, older projects will not function in Release 9. You should back up your project files, then create a new project using File/New->Project. After selecting the vendor and family, add your existing schematic (.DSN) and/or VHDL source files into the new project.

Use this procedure to migrate designs (.DSN) captured in Version 7.20 or earlier into Release 9:

1. Create a new project in Release 9.

2. Add the schematic (.DSN) and/or VHDL source files from the old project into the new project.

3. Use Replace Cache on all parts.

4. Check and repair disconnected pins.

5. Refer to the interface issues specific to the target vendor in these release notes.

This section describes issues regarding the Express interface to Actel place and route software.

• The Express Build command has been verified with Actel Designer Series R2-1998.

• Schematic-based projects for Actel developed with Express for Windows Version 7.20 should be migrated using the guidelines described in Migrating Express projects from previous releases to Express Release 9.

• Schematic libraries for Actel have been reorganized and unified. The following schematic libraries are no longer included in the configuration performed by the programmable logic project wizard:
  • ACT1 family: SOFT.OLB

  • ACT2/1200XL family: A12SOFT1.OLB, A12SOFT2.OLB

  • ACT3/1240XL family: A14SOFT1.OLB, A14SOFT2.OLB

  • 3200DX family: A32SOFT1.OLB, A32SOFT2.OLB

  These libraries are not obsolete, but Actel recommends that macros created by Actel ACTgen are preferred and will produce superior results. See Designing with ACTgen macros in the Express online help for more information.

This section describes issues regarding the Express interface to Altera fitter software.

• The Express Build command has been verified with Altera MAX+PLUS II Version 9.1.

• Schematic-based projects for Altera developed with Express for Windows Version 7.20 should be migrated using the guidelines described in Migrating Express projects from previous releases to Express Release 9. The macros CBUF, AND2-AND12, OR2-OR12, INV, EXP, LCELL, SOFT, GLOBAL, and XOR2 have been modified.

• The Altera Classic family support is now part of the Simple PLD support. Altera EPLDs developed using Altera projects should be migrated to Simple PLD projects.

This section describes issues regarding the Express interface to Lattice fitter software.

• The Express Build command has been verified with Lattice Semiconductor pDS+ Version 5.1.

• Release 9 supports the 1000, 2000, and 3000 families of pLSI/ispLSI devices. To target 5000 or 8000 families, create a Lattice pLSI/ispLSI project; however, some design entry elements and simulation models supported by these families are not available.

This section describes issues regarding the Express interface to Lucent place and route software.

• The Express Build command has been verified with Lucent ORCA Foundry Version 9.3.

• ORCA 3C/3T support is available only in Express Plus.

• ORCA uses the FlexLM locking scheme and expects the license file to be in the Lucent directory. Xilinx Alliance Series (M1) software also uses FlexLM, but does not require that the license file be in a particular directory. If you run both tools, combine the license file and place it in the Lucent directory.

This section describes issues regarding the Express interface to Philips fitter software.

• The Express Build command is compatible with Philips Semiconductor XPLA Designer XL 3.1 or later.

• If Express cannot locate the XPLA interface when you run the Build command, make sure the XPLA.INI subdirectory is included in your system path.

• The Generate Part command does not provide an interface for Philips XPLA; however, you can modify the project.FIT report into a compatible format similar to the Actel Pin File format (with the extension .PNE).

  Example XPLA Fitter report (.FIT):
  

  DESIGN : online
  DEVICE : pz3032-8a44
  FITTER : xplafitversion 3.10
  DATE : Nov 16 16:11:18 1998
  $DEVICE pz3032-8a44 fit
  $PINS 21
  DFFREIN : 5
  XR2IN : 4
  CLK : 43
  QOUT : 39
  XR2OUT: 38
  

  Example modified for Generate Part (.PNE):
  

  ; HEADER
  PIN DFFREIN;
    PIN:5.
  PIN XR2IN;
    PIN:4.
  PIN CLK;
    PIN:43.
  PIN QOUT;
    PIN:39.
  PIN XR2OUT;
    PIN:38.

This section describes issues regarding the Express interface to the OrCAD PLD fitter software.

• If you choose the Custom installation option of Express, be sure to enable the PCB Libraries: TTL_VHDL model resources component of the Custom Libraries installation. PLAGATES.VHD is required for Timed simulation of Simple PLD projects..

This section describes issues regarding the Express interface to Vantis MACHXL software.

• The Express Build command has been verified with Vantis MACHXL Version 5.4.

• If you choose the Custom installation option of Express, be sure to enable the PCB Libraries: TTL_VHDL model resources component of the Custom Libraries installation. ORCOMP.VHD is required for In Design simulation of Vantis projects that include components from the AMD_LS.OLB schematic library.

This section describes issues regarding the Express interface to Xilinx Alliance Series place and route software.

• The Express Build command has been verified with Xilinx Alliance Series vA1.5.

• Schematic libraries for Xilinx have been reorganized and unified. The following schematic libraries are no longer included in the configuration performed by the programmable logic project wizard:
  • XC3x00A/L family: XC3X00.OLB

  • XC4000E/L family: XC4000E.OLB

  • XC4000X family: XC4000X.OLB

  • XC5200 family: XC5200.OLB

  • XC9500 family: XC9500.OLB

  Instead Xilinx Unified Library macros which are portable across device families are consolidated into XUNIFIED.OLB. For more information see the online help topic Designing entry for Xilinx Alliance Series (M1) designs in the Express online help .

• Xilinx Virtex support. Since support for this architecture is in its first release, it is advisable to check the Xilinx and OrCAD web sites for the latest updates. Back annotation is not currently supported. Support for creating bitstreams for the Virtex devices will be provided when devices are available. Schematic entry libraries are not available.

• TIMESPEC and TIMEGRP parts are not supported via schematic entry. OrCAD recommends using the Xilinx Constraints Editor to group elements or specify timing requirements.

• When compiling Xilinx projects, on the Xilinx Technology tab of the Express Compiler Options dialog box, you must use lower case letters to assign GSR entry.

• If you install new FPGA speed-grade or package support after you install Release 9, the new devices may not appear in the Part name list of the General tab of the Xilinx Alliance Series Build Settings dialog box. To update the list, run the Xilinx tool PARTGEN -p from the command line. Copy the new parts list (PARTLIST.XCT) to the `\ORCAD\CAPTURE\LIBRARY\XIL_M1 subdirectory. You can also manually specify the package name.

• Models which cause load time errors: CC16CLED. Please check the OrCAD website for updates.

• Express Plus only: Place and route of some VHDL-based projects may exhibit unexpected removal of reset logic if the Max Fanout entry is set less than 16. Timed simulations will not operate as expected. The work around is to adjust the Output format to Xilinx Netlist Format (XNF) and run Xilinx A1 independently of the Build tool.

• ORCA uses the FlexLM locking scheme and expects the license file to be in the Lucent directory. Xilinx Alliance Series (M1) software also uses FlexLM, but does not require that the license file be in a particular directory. If you run both tools, combine the license file and place it in the Lucent directory.

This section describes issues regarding the Express interface to XACTStep v5/v6 place and route software.

• The Express Build command has been verified with Xilinx XACTStep v5/v6.

• Schematic-based projects for Xilinx developed with Express for Windows Version 7.20 should be migrated using the guidelines described in Migrating Express projects from previous releases to Express Release 9.

• TIMESPEC and TIMEGRP parts are not supported via schematic entry. OrCAD recommends using a constraint file (design_name.cst) to control the implementation of your design. The constraint file can contain information on where to place I/O pins and blocks of logic (FPGA only), and timing requirements for the design.