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Overview Resources Used 1   Processing System 1   AXI Interconnect 1   AXI General Purpose IO 1   CODEC_INTERFACE Specifics Generated Mon Mar 24 19:03:59 2014 EDK Version 14.3 Device Family zynq Device xc7z020clg484-1

Block Diagram TOP

External Ports TOP These are the external ports defined in the MHS file. Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  # NAME DIR [LSB:MSB] SIG ATTRIBUTES codec_interface_0 AC_GPIO1 I 1 AC_GPIO1_in codec_interface_0 AC_GPIO2 I 1 AC_GPIO2_in codec_interface_0 AC_GPIO3 I 1 AC_GPIO3_in codec_interface_0 enable I 1 enable_in codec_interface_0 rec I 1 rec_in codec_interface_0 AC_SDA IO 1 AC_SDA_inout codec_interface_0 AC_ADR0 O 1 AC_ADR0_out codec_interface_0 AC_ADR1 O 1 AC_ADR1_out codec_interface_0 AC_GPIO0 O 1 AC_GPIO0_out codec_interface_0 AC_MCLK O 1 AC_MCLK_out codec_interface_0 AC_SCK O 1 AC_SCK_out codec_interface_0 l_enable O 1 l_enable_out codec_interface_0 l_play O 1 l_play_out codec_interface_0 l_rec O 1 l_rec_out processing_system7_0 processing_system7_0_PS_CLK_pin I 1 processing_system7_0_PS_CLK  CLK  processing_system7_0 processing_system7_0_PS_PORB_pin I 1 processing_system7_0_PS_PORB processing_system7_0 processing_system7_0_PS_SRSTB_pin I 1 processing_system7_0_PS_SRSTB processing_system7_0 processing_system7_0_DDR_Addr IO 0:14 processing_system7_0_DDR_Addr processing_system7_0 processing_system7_0_DDR_BankAddr IO 0:2 processing_system7_0_DDR_BankAddr processing_system7_0 processing_system7_0_DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n processing_system7_0 processing_system7_0_DDR_CKE IO 1 processing_system7_0_DDR_CKE processing_system7_0 processing_system7_0_DDR_CS_n IO 1 processing_system7_0_DDR_CS_n processing_system7_0 processing_system7_0_DDR_Clk IO 1 processing_system7_0_DDR_Clk  CLK  processing_system7_0 processing_system7_0_DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n  CLK  processing_system7_0 processing_system7_0_DDR_DM IO 0:3 processing_system7_0_DDR_DM processing_system7_0 processing_system7_0_DDR_DQ IO 0:31 processing_system7_0_DDR_DQ processing_system7_0 processing_system7_0_DDR_DQS IO 0:3 processing_system7_0_DDR_DQS processing_system7_0 processing_system7_0_DDR_DQS_n IO 0:3 processing_system7_0_DDR_DQS_n processing_system7_0 processing_system7_0_DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB  RESET  processing_system7_0 processing_system7_0_DDR_ODT IO 1 processing_system7_0_DDR_ODT processing_system7_0 processing_system7_0_DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n processing_system7_0 processing_system7_0_DDR_VRN IO 1 processing_system7_0_DDR_VRN processing_system7_0 processing_system7_0_DDR_VRP IO 1 processing_system7_0_DDR_VRP processing_system7_0 processing_system7_0_MIO IO 0:53 processing_system7_0_MIO processing_system7_0 processing_system7_0_DDR_WEB_pin O 1 processing_system7_0_DDR_WEB Unconnected play I 1 gpio_data_in[0] Unconnected calc I 1 gpio_data_in[3]

Processors TOP processing_system7_0   Processing System Processing System wrapper for Series 7 IP Specs Core Version Documentation processing_system7 4.02.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 MIO IO 1 processing_system7_0_MIO 1 PS_SRSTB I 1 processing_system7_0_PS_SRSTB 2 PS_CLK I 1 processing_system7_0_PS_CLK 3 PS_PORB I 1 processing_system7_0_PS_PORB 4 DDR_Clk IO 1 processing_system7_0_DDR_Clk 5 DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n 6 DDR_CKE IO 1 processing_system7_0_DDR_CKE 7 DDR_CS_n IO 1 processing_system7_0_DDR_CS_n 8 DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n 9 DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n 10 DDR_WEB O 1 processing_system7_0_DDR_WEB 11 DDR_BankAddr IO 1 processing_system7_0_DDR_BankAddr 12 DDR_Addr IO 1 processing_system7_0_DDR_Addr 13 DDR_ODT IO 1 processing_system7_0_DDR_ODT 14 DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB 15 DDR_DQ IO 1 processing_system7_0_DDR_DQ 16 DDR_DM IO 1 processing_system7_0_DDR_DM 17 DDR_DQS IO 1 processing_system7_0_DDR_DQS 18 DDR_DQS_n IO 1 processing_system7_0_DDR_DQS_n 19 DDR_VRN IO 1 processing_system7_0_DDR_VRN 20 DDR_VRP IO 1 processing_system7_0_DDR_VRP 21 FCLK_CLK0 O 1 processing_system7_0_FCLK_CLK0 22 FCLK_RESET0_N O 1 processing_system7_0_FCLK_RESET0_N 23 M_AXI_GP0_ACLK I 1 processing_system7_0_FCLK_CLK0 24 IRQ_F2P I 1 axi_gpio_0_IP2INTC_Irpt Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To M_AXI_GP0 MASTER AXI axi_interconnect_1 2 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_EN_EMIO_CAN0 0 C_EN_EMIO_CAN1 0 C_EN_EMIO_ENET0 0 C_EN_EMIO_ENET1 0 C_EN_EMIO_GPIO 0 C_EN_EMIO_I2C0 0 C_EN_EMIO_I2C1 0 C_EN_EMIO_PJTAG 0 C_EN_EMIO_SDIO0 0 C_EN_EMIO_CD_SDIO0 0 C_EN_EMIO_WP_SDIO0 0 C_EN_EMIO_SDIO1 0 C_EN_EMIO_CD_SDIO1 0 C_EN_EMIO_WP_SDIO1 0 C_EN_EMIO_SPI0 0 C_EN_EMIO_SPI1 0 C_EN_EMIO_UART0 0 C_EN_EMIO_UART1 0 C_EN_EMIO_MODEM_UART0 0 C_EN_EMIO_MODEM_UART1 0 C_EN_EMIO_TTC0 1 C_EN_EMIO_TTC1 0 C_EN_EMIO_WDT 0 C_EN_EMIO_TRACE 0 C_USE_M_AXI_GP0 1 C_USE_M_AXI_GP1 0 C_USE_S_AXI_GP0 0 C_USE_S_AXI_GP1 0 C_USE_S_AXI_ACP 0 C_USE_S_AXI_HP0 0 C_USE_S_AXI_HP1 0 C_USE_S_AXI_HP2 0 C_USE_S_AXI_HP3 0 C_S_AXI_GP0_ENABLE_LOWOCM_DDR 0 C_S_AXI_GP1_ENABLE_LOWOCM_DDR 0 C_S_AXI_ACP_ENABLE_HIGHOCM 0 C_S_AXI_HP0_ENABLE_HIGHOCM 0 C_S_AXI_HP1_ENABLE_HIGHOCM 0 C_S_AXI_HP2_ENABLE_HIGHOCM 0 C_S_AXI_HP3_ENABLE_HIGHOCM 0 C_USE_DMA0 0 C_USE_DMA1 0 C_USE_DMA2 0 C_USE_DMA3 0 C_USE_TRACE 0 C_INCLUDE_TRACE_BUFFER 0 C_TRACE_BUFFER_FIFO_SIZE 128 USE_TRACE_DATA_EDGE_DETECTOR 0 C_TRACE_BUFFER_CLOCK_DELAY 12 C_USE_CROSS_TRIGGER 0 C_USE_CR_FABRIC 1 C_USE_AXI_FABRIC_IDLE 0 C_USE_DDR_BYPASS 0 C_USE_FABRIC_INTERRUPT 1 C_USE_PROC_EVENT_BUS 0 C_EN_EMIO_SRAM_INT 0 C_EMIO_GPIO_WIDTH 64 C_INCLUDE_ACP_TRANS_CHECK 0 C_USE_DEFAULT_ACP_USER_VAL 0 C_S_AXI_ACP_ARUSER_VAL 31 C_S_AXI_ACP_AWUSER_VAL 31 C_DQ_WIDTH 32 C_DQS_WIDTH 4 C_DM_WIDTH 4 C_MIO_PRIMITIVE 54 C_PACKAGE_NAME clg484 C_PS7_SI_REV PRODUCTION C_UART_BAUD_RATE 115200 C_DDR_RAM_BASEADDR 0x00000000 C_DDR_RAM_HIGHADDR 0x1FFFFFFF C_UART0_BASEADDR 0xE0000000 C_UART0_HIGHADDR 0xE0000FFF C_UART1_BASEADDR 0xE0001000 C_UART1_HIGHADDR 0xE0001FFF C_I2C0_BASEADDR 0xE0004000 C_I2C0_HIGHADDR 0xE0004FFF C_I2C1_BASEADDR 0xE0005000 C_I2C1_HIGHADDR 0xE0005FFF C_SPI0_BASEADDR 0xE0006000 C_SPI0_HIGHADDR 0xE0006FFF C_SPI1_BASEADDR 0xE0007000 C_SPI1_HIGHADDR 0xE0007FFF C_CAN0_BASEADDR 0xE0008000 C_CAN0_HIGHADDR 0xE0008FFF C_CAN1_BASEADDR 0xE0009000 C_CAN1_HIGHADDR 0xE0009FFF C_GPIO_BASEADDR 0xE000A000 C_GPIO_HIGHADDR 0xE000AFFF C_ENET0_BASEADDR 0xE000B000 C_ENET0_HIGHADDR 0xE000BFFF C_ENET1_BASEADDR 0xE000C000 C_ENET1_HIGHADDR 0xE000CFFF C_SDIO0_BASEADDR 0xE0100000 C_SDIO0_HIGHADDR 0xE0100FFF C_SDIO1_BASEADDR 0xE0101000 C_SDIO1_HIGHADDR 0xE0101FFF C_USB0_BASEADDR 0xE0102000 C_USB0_HIGHADDR 0xE0102FFF C_USB1_BASEADDR 0xE0103000 C_USB1_HIGHADDR 0xE0103FFF C_TTC0_BASEADDR 0xE0104000 C_TTC0_HIGHADDR 0xE0104FFF C_TTC1_BASEADDR 0xE0105000 C_TTC1_HIGHADDR 0xE0105FFF C_M_AXI_GP0_PROTOCOL AXI3 C_M_AXI_GP0_ID_WIDTH 12 C_M_AXI_GP0_ADDR_WIDTH 32 C_M_AXI_GP0_DATA_WIDTH 32 C_M_AXI_GP0_ENABLE_STATIC_REMAP 0 C_M_AXI_GP0_SUPPORTS_NARROW_BURST 0 C_M_AXI_GP0_SUPPORTS_REORDERING 0 C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING 8 C_INTERCONNECT_M_AXI_GP0_READ_ISSUING 8 C_M_AXI_GP1_PROTOCOL AXI3 C_M_AXI_GP1_ID_WIDTH 12 C_M_AXI_GP1_ADDR_WIDTH 32 C_M_AXI_GP1_DATA_WIDTH 32 Name Value C_M_AXI_GP1_ENABLE_STATIC_REMAP 0 C_M_AXI_GP1_SUPPORTS_NARROW_BURST 0 C_M_AXI_GP1_SUPPORTS_REORDERING 0 C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING 8 C_INTERCONNECT_M_AXI_GP1_READ_ISSUING 8 C_S_AXI_GP0_PROTOCOL AXI3 C_S_AXI_GP0_ID_WIDTH 6 C_S_AXI_GP0_ADDR_WIDTH 32 C_S_AXI_GP0_DATA_WIDTH 32 C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE 8 C_S_AXI_GP1_PROTOCOL AXI3 C_S_AXI_GP1_ID_WIDTH 6 C_S_AXI_GP1_ADDR_WIDTH 32 C_S_AXI_GP1_DATA_WIDTH 32 C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE 8 C_S_AXI_ACP_PROTOCOL AXI3 C_S_AXI_ACP_ID_WIDTH 3 C_S_AXI_ACP_ADDR_WIDTH 32 C_S_AXI_ACP_DATA_WIDTH 64 C_S_AXI_ACP_SUPPORTS_USER_SIGNALS 1 C_S_AXI_ACP_ARUSER_WIDTH 5 C_S_AXI_ACP_AWUSER_WIDTH 5 C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE 8 C_S_AXI_HP0_PROTOCOL AXI3 C_S_AXI_HP0_ID_WIDTH 6 C_S_AXI_HP0_ADDR_WIDTH 32 C_S_AXI_HP0_DATA_WIDTH 64 C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE 8 C_S_AXI_HP1_PROTOCOL AXI3 C_S_AXI_HP1_ID_WIDTH 6 C_S_AXI_HP1_ADDR_WIDTH 32 C_S_AXI_HP1_DATA_WIDTH 64 C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE 8 C_S_AXI_HP2_PROTOCOL AXI3 C_S_AXI_HP2_ID_WIDTH 6 C_S_AXI_HP2_ADDR_WIDTH 32 C_S_AXI_HP2_DATA_WIDTH 64 C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE 8 C_S_AXI_HP3_PROTOCOL AXI3 C_S_AXI_HP3_ID_WIDTH 6 C_S_AXI_HP3_ADDR_WIDTH 32 C_S_AXI_HP3_DATA_WIDTH 64 C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE 8 C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE 8 C_S_AXI_GP0_BASEADDR 0xE0000000 C_S_AXI_GP0_HIGHADDR 0xFFFFFFFF C_S_AXI_GP0_LOWOCM_DDR_BASEADDR 0x00000000 C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF C_S_AXI_GP1_BASEADDR 0xE0000000 C_S_AXI_GP1_HIGHADDR 0xFFFFFFFF C_S_AXI_GP1_LOWOCM_DDR_BASEADDR 0x00000000 C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF C_S_AXI_ACP_BASEADDR 0x00000000 C_S_AXI_ACP_HIGHADDR 0x3FFFFFFF C_S_AXI_ACP_HIGHOCM_BASEADDR 0xFFFC0000 C_S_AXI_ACP_HIGHOCM_HIGHADDR 0xFFFFFFFF C_S_AXI_HP0_BASEADDR 0x00000000 C_S_AXI_HP0_HIGHADDR 0x3FFFFFFF C_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000 C_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFFFF C_S_AXI_HP1_BASEADDR 0x00000000 C_S_AXI_HP1_HIGHADDR 0x3FFFFFFF C_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000 C_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFFFF C_S_AXI_HP2_BASEADDR 0x00000000 C_S_AXI_HP2_HIGHADDR 0x3FFFFFFF C_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000 C_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFFFF C_S_AXI_HP3_BASEADDR 0x00000000 C_S_AXI_HP3_HIGHADDR 0x3FFFFFFF C_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000 C_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFFFF C_M_AXI_GP0_SUPPORTS_THREADS 1 C_M_AXI_GP0_THREAD_ID_WIDTH 12 C_M_AXI_GP1_SUPPORTS_THREADS 1 C_M_AXI_GP1_THREAD_ID_WIDTH 12 C_NUM_F2P_INTR_INPUTS 2 C_EN_DDR 1 C_EN_SMC 0 C_EN_QSPI 1 C_EN_CAN0 0 C_EN_CAN1 0 C_EN_ENET0 1 C_EN_ENET1 0 C_EN_GPIO 1 C_EN_I2C0 0 C_EN_I2C1 0 C_EN_PJTAG 0 C_EN_SDIO0 1 C_EN_SDIO1 0 C_EN_SPI0 0 C_EN_SPI1 0 C_EN_UART0 0 C_EN_UART1 1 C_EN_MODEM_UART0 0 C_EN_MODEM_UART1 0 C_EN_TTC0 1 C_EN_TTC1 0 C_EN_WDT 0 C_EN_TRACE 0 C_EN_USB0 1 C_EN_USB1 0 C_EN_4K_TIMER 0 C_FCLK_CLK0_FREQ 47619049 C_FCLK_CLK1_FREQ 142857132 C_FCLK_CLK2_FREQ 50000000 C_FCLK_CLK3_FREQ 50000000 C_FCLK_CLK0_BUF TRUE C_FCLK_CLK1_BUF TRUE C_FCLK_CLK2_BUF TRUE C_FCLK_CLK3_BUF TRUE Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Busses TOP axi_interconnect_1   AXI Interconnect AXI4 Memory-Mapped Interconnect IP Specs Core Version Documentation axi_interconnect 1.06.a IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 INTERCONNECT_ACLK I 1 processing_system7_0_FCLK_CLK0 1 INTERCONNECT_ARESETN I 1 processing_system7_0_FCLK_RESET0_N Bus Connections INSTANCE INTERFACE TYPE INTERFACE NAME processing_system7_0 MASTER M_AXI_GP0 axi_gpio_0 SLAVE S_AXI codec_interface_0 SLAVE S_AXI Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY rtl C_BASEFAMILY rtl C_NUM_SLAVE_SLOTS 1 C_NUM_MASTER_SLOTS 1 C_AXI_ID_WIDTH 1 C_AXI_ADDR_WIDTH 32 C_AXI_DATA_MAX_WIDTH 32 C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 C_INTERCONNECT_DATA_WIDTH 32 C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_IS_INTERCONNECT 0b0000000000000000 C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000 C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000 C_INTERCONNECT_ACLK_RATIO 1 C_S_AXI_SUPPORTS_WRITE 0b1111111111111111 C_S_AXI_SUPPORTS_READ 0b1111111111111111 C_M_AXI_SUPPORTS_WRITE 0b1111111111111111 C_M_AXI_SUPPORTS_READ 0b1111111111111111 C_AXI_SUPPORTS_USER_SIGNALS 0 C_AXI_AWUSER_WIDTH 1 C_AXI_ARUSER_WIDTH 1 C_AXI_WUSER_WIDTH 1 C_AXI_RUSER_WIDTH 1 C_AXI_BUSER_WIDTH 1 C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF C_S_AXI_SINGLE_THREAD 0b0000000000000000 C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111 C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111 C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111 C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 Name Value C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_SECURE 0b0000000000000000 C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111 C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000 C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_READ_FIFO_TYPE 0b1111111111111111 C_S_AXI_READ_FIFO_DELAY 0b0000000000000000 C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111 C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000 C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_READ_FIFO_TYPE 0b1111111111111111 C_M_AXI_READ_FIFO_DELAY 0b0000000000000000 C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_INTERCONNECT_R_REGISTER 0 C_INTERCONNECT_CONNECTIVITY_MODE 0 C_USE_CTRL_PORT 0 C_USE_INTERRUPT 1 C_RANGE_CHECK 2 C_S_AXI_CTRL_PROTOCOL AXI4LITE C_S_AXI_CTRL_ADDR_WIDTH 32 C_S_AXI_CTRL_DATA_WIDTH 32 C_BASEADDR 0xFFFFFFFF C_HIGHADDR 0x00000000 C_DEBUG 0 C_S_AXI_DEBUG_SLOT 0 C_M_AXI_DEBUG_SLOT 0 C_MAX_DEBUG_THREADS 1   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Peripherals TOP axi_gpio_0   AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. IP Specs Core Version Documentation axi_gpio 1.01.b IP PORT LIST These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0 1 GPIO_IO_I I 1 gpio_data_in 2 GPIO2_IO_O O 1 play_in 3 IP2INTC_Irpt O 1 axi_gpio_0_IP2INTC_Irpt Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To S_AXI SLAVE AXI axi_interconnect_1 2 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY virtex6 C_INSTANCE axi_gpio_inst C_BASEADDR 0x41200000 C_HIGHADDR 0x4120FFFF C_S_AXI_ADDR_WIDTH 9 C_S_AXI_DATA_WIDTH 32 C_GPIO_WIDTH 4 C_GPIO2_WIDTH 1 C_ALL_INPUTS 1 Name Value C_ALL_INPUTS_2 0 C_INTERRUPT_PRESENT 1 C_DOUT_DEFAULT 0x00000000 C_TRI_DEFAULT 0xFFFFFFFF C_IS_DUAL 1 C_DOUT_DEFAULT_2 0x00000000 C_TRI_DEFAULT_2 0xFFFFFFFF C_S_AXI_PROTOCOL AXI4LITE   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. codec_interface_0   CODEC_INTERFACE interface for the external codec device IP Specs Core Version codec_interface 1.00.a PORT LIST These are the ports listed in the MHS file. # NAME DIR [LSB:MSB] SIGNAL 0 S_AXI_ACLK I 1 processing_system7_0_FCLK_CLK0 1 enable I 1 enable_in 2 rec I 1 rec_in 3 play I 1 play_in 4 buffer_r_ready O 1 gpio_data_in[1] 5 buffer_w_ready O 1 gpio_data_in[2] 6 l_enable O 1 l_enable_out 7 l_rec O 1 l_rec_out 8 l_play O 1 l_play_out 9 AC_ADR0 O 1 AC_ADR0_out 10 AC_ADR1 O 1 AC_ADR1_out 11 AC_GPIO0 O 1 AC_GPIO0_out 12 AC_GPIO1 I 1 AC_GPIO1_in 13 AC_GPIO2 I 1 AC_GPIO2_in 14 AC_GPIO3 I 1 AC_GPIO3_in 15 AC_MCLK O 1 AC_MCLK_out 16 AC_SDA IO 1 AC_SDA_inout 17 AC_SCK O 1 AC_SCK_out Bus Interfaces  NAME   TYPE  BUSSTD BUS Connected To S_AXI SLAVE AXI axi_interconnect_1 2 Peripherals. Parameters These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_S_AXI_DATA_WIDTH 32 C_S_AXI_ADDR_WIDTH 32 C_S_AXI_MIN_SIZE 0x000001FF C_USE_WSTRB 0 C_DPHASE_TIMEOUT 8 C_BASEADDR 0x6C000000 C_HIGHADDR 0x6C00FFFF Name Value C_FAMILY virtex6 C_NUM_REG 4 C_NUM_MEM 1 C_SLV_AWIDTH 32 C_SLV_DWIDTH 32 C_S_AXI_PROTOCOL AXI4LITE   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Timing Information TOP Post Synthesis Clock Limits No clocks could be identified in the design. Run platgen to generate synthesis information.