Project Status (01/25/2011 - 12:14:18)
Project File: system.xmp Implementation State: Programming File Generated
Module Name: system
  • Errors:
 
Product Version:EDK 12.3
  • Warnings:
 
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log Filemar 25. ene 11:50:05 2011018 Warnings (18 new)23 Infos (23 new)
Libgen Log Filemar 25. ene 12:13:00 2011000
Simgen Log File    
BitInit Log Filemar 25. ene 12:14:19 20110013 Infos (13 new)
System Log Filemar 25. ene 12:14:19 2011   
 
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemmar 25. ene 11:50:31 201121653150160
fsl_v20_0_wrappermar 25. ene 11:49:34 2011744 0
generador_0_wrappermar 25. ene 11:49:23 201199164 0
proc_sys_reset_0_wrappermar 25. ene 11:49:08 20116953 0
mdm_0_wrappermar 25. ene 11:48:49 2011126148 0
clock_generator_0_wrappermar 25. ene 11:47:44 20114  0
flash_2mx16_wrappermar 25. ene 11:47:37 2011472382 0
cs_push_3bit_wrappermar 25. ene 11:45:58 20119055 0
usb_uart_wrappermar 25. ene 11:44:11 2011143132 0
lmb_bram_wrappermar 25. ene 11:42:35 2011  160
ilmb_cntlr_wrappermar 25. ene 11:42:14 201126 0
dlmb_cntlr_wrappermar 25. ene 11:42:00 201126 0
dlmb_wrappermar 25. ene 11:41:51 201111 0
ilmb_wrappermar 25. ene 11:41:44 201111 0
mb_plb_wrappermar 25. ene 11:41:22 2011155382 0
microblaze_0_wrappermar 25. ene 11:39:22 20119941776 0
 
Device Utilization Summary (actual values) [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,605 7,168 22%  
Number of 4 input LUTs 2,527 7,168 35%  
Number of occupied Slices 1,829 3,584 51%  
    Number of Slices containing only related logic 1,829 1,829 100%  
    Number of Slices containing unrelated logic 0 1,829 0%  
Total Number of 4 input LUTs 2,617 7,168 36%  
    Number used as logic 2,097      
    Number used as a route-thru 90      
    Number used for Dual Port RAMs 256      
    Number used as Shift registers 174      
Number of bonded IOBs 57 195 29%  
    IOB Flip Flops 74      
Number of BUFGMUXs 4 24 16%  
Number of DCMs 1 4 25%  
Number of BSCANs 1 1 100%  
Number of BSCAN_SPARTAN3As 1 1 100%  
Number of MULT18X18SIOs 3 20 15%  
Number of RAMB16BWEs 16 20 80%  
Average Fanout of Non-Clock Nets 3.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrentmar 25. ene 11:51:05 2011016 Warnings (16 new)1 Info (1 new)
Map ReportCurrentmar 25. ene 11:52:15 2011   
Place and Route ReportCurrentmar 25. ene 11:52:58 201103 Warnings (3 new)0
Post-PAR Static Timing ReportCurrentmar 25. ene 11:53:08 2011004 Infos (4 new)
Bitgen ReportCurrentmar 25. ene 11:53:27 2011032 Warnings (32 new)1 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentmar 25. ene 11:53:29 2011

Date Generated: 01/25/2011 - 12:14:24